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作者 wait 在 PTT [ Electronics ] 看板的留言(推文), 共64則
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1F推: 1.單純看netlist .SUBKT I/O port比較design看看04/22 12:15
5F推: 1.Vlh = 0.9 Vhl = 0.65 threshold 0.8 或者 corner差異04/18 13:22
6F→: 2.clk crosstalk or coupling, 關掉clk後delay一下再測?04/18 13:26
1F推: 電表跟探棒也有內阻呀... V = IR 想辦法換算量??03/17 14:57
32F推: C/C++學越好Verilog"起步"就越難學,因為電路是parallel運作03/14 23:58
33F→: 但又如同C/C++以時間軸可作sequence的事情03/15 00:01
34F→: 全華 黃英叡 江文啟這本還行呀...至少現在工作中跟前輩們03/15 00:07
35F→: 不約而同都是同一本XD03/15 00:07
7F推: 錫膏不是都弄成針筒狀就好嗎XD 插個針頭 退冰就能上了XD03/08 12:30
8F推: 冰凍三尺 非一日之寒...02/23 12:18
2F推: 有dumpfile vcd檔+dumpvars,開waveform拉訊號看看??10/27 23:48
4F→: 同上+ 你把時間順序拿來看 先第三block 然後cnt=3 第二block10/08 12:34
5F→: 動作 最後第一block 負緣動作,所以setup T= 前面兩個動作10/08 12:36
6F→: result 是否會敲到第一FF SDF的setup T10/08 12:42
8F→: FF的Din值變了,拉該顆FF的CP&D 訊號出來看,trace D path10/07 12:13
8F推: Ans: Yes08/31 10:04