[問題] Verilog multi dimension arrays
在一本verilog實務設計的書上有看到它支援多維陣列
請問這是可以合成的嗎?
我是否可以做以下宣告:
reg [1:0]c[0:1];
reg [1:0]a[0:1];
reg [1:0]b[0:1];//都是寬度、大小為2的陣列
然後用for回圈assign
c[i]<=a[i]+b[i];
我在工作站用system verilog compiler是可以過
但是用verdi看波形圖時,居然找不到a、b和c
可否請問各位先進小弟這個用法是否有誤,謝謝
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※ 編輯: hardman1110 來自: 114.42.215.89 (09/26 23:46)
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