Re: [問題] design compiler後counter(計數器)總是 …
※ 引述《zxvc (眾生都是未來佛)》之銘言:
: ※ 引述《zxvc (眾生都是未來佛)》之銘言:
[恕刪]
: 上面這一句話不正確。事實上DFT Compiler真的可以產生這種各clock domain
: 各自串scan chain的方法。也就是這個指令:
: set_scan_configuration -clock_mixing no_mix
: (要配合這使用:
: set_dft_configuration -fix_clock enable
: )
: 然後DFT Compiler會幫不同的chain各自產生一個toplevel port,
: 作為不同clock的輸入。
: 那些clock ports是要接到如測試機台的clock generator,
: 也就是說在testing時,除頻的clock不是chip內部DFF除頻器產生的。
: 而這些clocks是用多工器接到原先
: functional mode circuit的clock pins上。
: 比如說有個DFF,在functional mode是用內部DFF除頻器作clock,
: 在testing mode是用測試機台的clock,所以要用多工器去選。
: 所以說DFT Compiler並不是完全不能處理DFF除頻器。
您說的case是 Stuck at fault :
每條 scan 的 clk 是外灌的,當然不同chain就會有不同scan clk
而同一條 chain在 Shift In /Capture/Shift Out時,
都是用同一個外灌的 scan clk
基本上,這個case不會遇到太多麻煩...
但是at speed 的話 :
同一條 chain,在 shift in/shift out時,是用 scan clk (外灌的)
可是在launch/capture時,是用 normal clk
而一般 normal clk 大部份都用 PLL 除出來的
所以才會遇到麻煩...
: : [1] Synopsys Inc., "DFT Compiler Scan User Guide,"
: : Version C-2009.06, July 2009.
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