[理工] [計組] pipeline
張凡下冊 110頁 39題(1)
Loop: add $1, $2, $3
sub $2, $3, $1
lw $1, 0($2)
or $3, $2, $1
beq $2, $3, Loop
addi $1, $3, 2
sw $1, 0($2)
subi $2, $1, 2
If we assume that the branch decision can be made in the stage of ID and the
branch is eventually taen in this case, please show the multi-cycle graph of
the pipelining execution
請問這題要怎麼畫?
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張凡下冊 118頁 題47(1)
L1: addi $t0, $t0, 4
lw $s1, 0($t0)
sw $s1, 32($t0)
lw $t1, 64($t0)
slt $s0, $t1, $zero
bne $s0, $zero, L1
no forwarding unit, insert NOP
張凡的解答說 1 no-op behind bne 請問這是為什麼?
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張凡下冊 121頁 題51
lw $4, 50($7)
beq $1, $4, 3
add $5, $3, $4
sub $6, $4, $3
or $7, $5, $2
slt $8, $5, $6
5 pipeline stages and data forwarding capability
if this CPU uses "always assume branch not taken" strategy to handle
instruction but the branch is taken in this example, how many clock cycles
are required to complete this programe?
答案是(5-1)+3+2+1 = 10
請問是為什麼?
謝謝
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