Re: [請益] 關於除頻電路(verilog)
: wire CLKD2 = counter[0];
: always @(posedge CLK or negedge ARST_N) begin
: if (!ARST_N) counter <= 3'b0;
: else counter <= counter - 1;
: end
: reg CLKSEL_GlitchFree;
: always @(negedge CLK or negedge ARST_N) begin
: if (!ARST_N) CLKSEL_GlitchFree <= 1'b0;
: else if (counter == 3'b000)
: CLKSEL_GlitchFree <= CLKSEL;
: end
: endmodule
請問有人會除2.5倍頻的電路嗎
duty可以不care
thanks
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