Re: [問題] 請問關於delay加法器的寫法
: reg shift_register[127:0];
: integer i ;
#########################################################
: always @ (posedge clk or negedge n_rst)begin
: if(!n_rst)begin
: shift_register <= 'b0 ;
: end
: else begin
: for(i=0 ; i<127 ; i=i+1)begin
: shifer_register[i+1] <=#(1) shifer_register[i] ;
: end
: end
: end
#########################################################
In the "#" segment, which can be coded in this way:
always @ ( posedge clk or negedgr n_rst)
begin
if (~n_rst) shift_register[127:0] <= 128'b0;
else shift_register[127:0] <= #1 {shift_register[126:0],in};
end
"in" is a signal from somewhere else.
That is it.
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