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作者 pierreqq 在 PTT [ Electronics ] 看板的留言(推文), 共18則

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Re: [問題] verilog 改成隨機輸入時為什麼沒輸出?

[ Electronics ]5 留言, 推噓總分: +3

作者: CompileUltra - 發表於 2010/04/06 22:55(15年前)

4^F推pierreqq:同意,我覺得他大概把電路寫出來然後放在altera裏去跑...04/16 15:16

5^F→pierreqq:除了砍掉重練,很難給他建議.. XD04/16 15:18

[問題] 請問一般四驅車的直流小馬達的額定電流是多少?

[ Electronics ]3 留言, 推噓總分: +1

作者: pierreqq - 發表於 2010/03/02 11:00(16年前)

2^F→pierreqq:感謝回應，這樣就放心了～03/02 13:17

Re: [問題] 關於verilog signal&varieble問題

[ Electronics ]8 留言, 推噓總分: +2

作者: zxvc - 發表於 2009/04/16 05:46(16年前)

1^F推pierreqq:你依ksmrt0123大提供那份文件的rule就沒錯了04/16 09:15

2^F→pierreqq:你們之間其實有共識,感覺是討論上的誤會... 哈哈04/16 09:16

7^F推pierreqq:嗯,你們倆的誤會就是這呀.. :D 沒強制限定哪種寫法的04/16 10:25

8^F→pierreqq:避開上面說的bad coding style就好了04/16 10:26

Re: [問題] 關於verilog signal&varieble問題

[ Electronics ]51 留言, 推噓總分: +11

作者: Acme - 發表於 2009/04/15 22:21(16年前)

33^F推pierreqq:col應該是指 IPQ 的 SIM.2 那條04/17 11:58

34^F→pierreqq:你們之前把com定為a+1,seq定會a<=1,所以討論起來很亂04/17 12:02

35^F→pierreqq:不自覺的一直鑽牛角尖下去04/17 12:03

36^F→pierreqq:com always-> block? seq always-> nonblocking?04/17 12:09

37^F→pierreqq:感覺像是表達上的失準04/17 12:13

38^F→pierreqq:大家都有經驗,應該不會卡在這種基本問題上才是04/17 12:14

[請益] 關於除頻電路(verilog)

[ Electronics ]9 留言, 推噓總分: +7

作者: maxwellee - 發表於 2009/04/15 17:31(16年前)

6^F推pierreqq:除2只有好選1了, 第2個是除4的電路...04/16 09:06

8^F推pierreqq:因為是assign clk2=ct[1]而不是assign clk2=ct[0]04/16 10:35

[問題] 請問用verilog如何測power

[ Electronics ]13 留言, 推噓總分: +3

作者: a000tt - 發表於 2008/11/12 17:54(17年前)

10^F→pierreqq:基本上是跑postsim,分析transition的次數11/13 09:28

11^F→pierreqq:我知道的可以用ncverilog跟DC power來達成11/13 09:29

[問題] 電流如何加乘 ?

[ Electronics ]2 留言, 推噓總分: +1

作者: dong812 - 發表於 2008/08/18 09:50(17年前)

2^F→pierreqq:並吧，輸出電流80mA，但單看馬達還是40mA08/19 11:11

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