[請益] FPGA(VHDL)實現雙輸入單輸出開關
大家好~
小弟第一次接觸FPGA,所以很多地方不懂
需要實現的電路圖如下面的網址:
http://imageshack.us/photo/my-images/828/ck13.jpg/
SIGNAL1 和SIGNAL2是輸入的訊號,兩顆MOS是用來當作開關
CK13 和 CK13-是用開控制開關的訊號,目的是要讓SINGAL1.2
分別在CK13 和CK13-輸出到VOUT,
是使用QUARTUS II作模擬,本來以為用內建的BLOCK就可以兜出來
不過後來這個部分沒有 MODEL可以叫,因此要採用VHDL來實現
目前我打得語法是:
library ieee;
use ieee.std_logic_1164.all;
entity swich2 is
port(sig1 : in std_logic;
sig2 : in std_logic;
ck13 : in std_logic;
ck132 : in std_logic;
vout : out std_logic);
end swich2;
architecture sig2 of swich2 is
begin
if ck13='1' then
vout<= sig1;
elsif ck132='1' then
vout<= sig2;
else
vout<='0';
end if;
end sig2;
請問是否有哪邊有問題呢?
沒有學過VHDL相關的課程= =~只能對著講義照感覺打@@
謝謝囉!!!
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