[問題] Xilinx CORE Generator IP請教
使用CORE Generator 產生所要的block RAM
在project 中顯示的為 "DualPortmMem4x6.xco" file
以下是DualPortmMem4x6.v裡的註解
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file DualPortmMem4x6.v when simulating
// the core, DualPortmMem4x6. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
如果我要使用DualPortmMem4x6.v這個 block RAM 在設計
請問一下我要如何compiler這個RAM
我找到的CORE Generator Help都是舊版的
ISE 9.2i
感謝
--
" 即使沒什麼苦惱不適,但只要反覆做著一樣的事情,
一次又一次,讓人厭倦已極,那就夠了.厭倦是身為人必有的本質.這是值得慶幸的."
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.112.48.70
推
05/05 16:36, , 1F
05/05 16:36, 1F
→
05/05 16:38, , 2F
05/05 16:38, 2F
→
05/05 16:41, , 3F
05/05 16:41, 3F
討論串 (同標題文章)