作者查詢 / ehrlich
作者 ehrlich 在 PTT [ Electronics ] 看板的留言(推文), 共45則
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1F推:你po-sim出來的電阻把 pl nd mark掉就可以了07/13 19:17
2F→:LPE default會把電阻在LVS裡的model name抽出來07/13 19:17
3F→:但若你在simulation沒使用特定res model 而只用ideal res07/13 19:17
4F→:那這些LVS的model name是沒用的07/13 19:18
3F推:改用PMOS design吧06/12 00:40
1F推:Hspice的 LX12~LX23 可以模擬MOS的端點電容 (Meyer model)06/03 14:04
2F推:我想 這還是個人對 "ic 設計排名的定義不同"的關係01/01 22:10
3F→:因為我所指的 正是林教授所講的 "營業額世界第二"01/01 22:11
4F→:至於其他人所認為的 甚至是否要包括Fab廠才算 都還有許01/01 22:12
5F→:多模糊地帶01/01 22:13
6F推:更何況 以Fabless來計算IC 設計能力 是目前的趨勢 若是01/01 22:19
7F→:要加上"自有Fab廠為條件來比較" 那是立足點不平等的比較01/01 22:20
8F→:自有Fab廠的vs自有Fab廠 Fabless vs. Fabless01/01 22:21
1F推:單端的OP似乎不需要CMFB的電路~~220.130.162.235 03/22