[理工] 100交大 計組
Assume that logic blocks needed to implement the datapath have the following
latencies: (Delays for other components are ignored. )
__________________________________________________________
I-Mem Add Mux ALU Regs D-Mem Sign-Ext shift-left2
__________________________________________________________
400 100 40 120 200 350 20 10
Compute the required delay time for each instruction and determine the minimum
cycle time of the computer.
張凡給的答案:
add: 400 +200+ 40+ 120+ 40+ 200 = 1000
I-Mem Regs Mux ALU Mux Regs(WB)
我的問題1:
為什麼 regDst這個Mux 不用考慮?
記得好像說是因為兩條路，一個有Mux一個沒有
可是ALuSrc這個Mux前面不是也是兩條路，一個有Mux一個沒有?但是ALuSrc這個Mux
卻要考慮?
我的問題2:
課本習題的這題好像不用考慮WB的時間，
為什麼交大這一題需要考慮?
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