[理工] 計組 99清大資工
Assume that a single cycle datapath with the critical path
of 10 ns can be partitioned into arbitary number of balanced
stages for pipelining , and there is no dependency between
instructions .
If the pipeling will introduce an addtional 1 ns delay to
each stage. What is the speed up for the 4-stage pipelined
datapath when compared with the single-cycle one?
-----------------------------------------------
answer :
The instruction time for a single-cycle machine = 10 ns
The instruction time for pipeline = (10 / 4) + 1 = 3.5 ns
^^^^^^^^^^^^why?
speedup = 10 / 3.5 = 2.86
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