Re: [理工] [計組] 98交大資工
看板Grad-ProbAsk作者charliejack (charliejack)時間15年前 (2011/02/11 09:20)推噓4(4推 0噓 7→)留言11則, 5人參與討論串2/2 (看更多)
※ 引述《boy5548 (小YO)》之銘言：
: Assume virtually addressed cache is used, is it possible to have TLB miss, but
: page table and cache hit for a data access? Please explain you answer.
這一題讓我想到台大97的一題
Cache: virtually-addressed but physically-tagged, 8KB, direct-mapped,
32B block size
TLB: full associative, 32 entries
32-bit phisical address
Virtual Memory: 8K page 64-bit virtual address
Why do we want to use a virtully-addressed but physically-tagged cache?
這題是因為 直接在Cache裡面做 做virtually-> physical的轉換
那TLB是幹麻的0.0?
之前 最簡單的TLB
就是用來 V->P 的轉換
第二部到Cache裡找資料
現在Cache自己有這個功能了~
So 到底是?
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