[理工] [計組]-成大97-資工所
題目:Assume that a processor implements the hardware TLB cache.
Assume also that the instruction and data caches are physical
address caches. The processor includes the write buffer into
its implementation.
(1)For executing an instruction, what is the maximal number of
cache misses that can be introduced to the processor?
(need not consider the misses due to the executions handling)
(2)What are these misses?
麻煩幫我解答一下 感謝!!
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