[問題] verilog coding style
想請問一下版上的板友
為什麼現在大家都推薦把non combinational/combination circuit分開寫呢?
用code來說的話
// coding style 1
always @(posedge clk or posedge reset)
begin
if (reset)
out <= 0;
else
out <= a*b;
end
// coding style 2
always @(*)
begin
next_out = a*b;
end
always @(posedge clk or posedge reset)
begin
if (reset)
out <= 0;
else
out <= next_out;
end
請問coding style 2 主要的好處是? (或coding style 1的壞處)
公司企業裡面也都使用coding style2 嗎?
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 118.160.231.59
→
11/04 10:34, , 1F
11/04 10:34, 1F
→
11/04 10:36, , 2F
11/04 10:36, 2F
→
11/04 10:37, , 3F
11/04 10:37, 3F
→
11/04 12:48, , 4F
11/04 12:48, 4F
→
11/04 12:48, , 5F
11/04 12:48, 5F
→
11/04 13:17, , 6F
11/04 13:17, 6F
→
11/04 13:19, , 7F
11/04 13:19, 7F
→
11/04 15:28, , 8F
11/04 15:28, 8F
→
11/04 15:30, , 9F
11/04 15:30, 9F
→
11/04 15:31, , 10F
11/04 15:31, 10F
討論串 (同標題文章)
以下文章回應了本文：
完整討論串 (本文為第 1 之 2 篇)：