[問題] VERILOG 時脈問題
always@(posedge clk or negedge reset )
begin
if(!reset)
begin
count=0;
end
else
begin
count1<=0;
buffer<=bufin;
count <=count+1;
begin
if(count==n)
begin
判斷<=1;
end
end
end
end
end
always@(posedge clk )
begin
if(判斷==0)
begin
bufout<= 1'bz;
end
else if(判斷==1)
begin
count <=0;
bufout<= buffer;
count1<=count1+1;
begin
if(count1==n)
判斷<=0;
end
end
end
endmodule
我這樣寫
實際的輸出結果會比我想要的輸出 "慢1個CLOCK"
請問是哪出問題?
也就是判斷==1 但bufout晚1個CLOCK出來
--
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◆ From: 59.117.162.75
※ 編輯: zx33571163 來自: 59.117.162.75 (08/15 21:59)
※ 編輯: zx33571163 來自: 59.117.162.75 (08/15 22:00)
推
08/15 22:51, , 1F
08/15 22:51, 1F
→
08/16 00:48, , 2F
08/16 00:48, 2F
推
08/16 08:23, , 3F
08/16 08:23, 3F
→
08/16 10:31, , 4F
08/16 10:31, 4F
→
08/16 10:37, , 5F
08/16 10:37, 5F
→
08/16 10:38, , 6F
08/16 10:38, 6F
→
08/16 10:40, , 7F
08/16 10:40, 7F
→
08/16 10:42, , 8F
08/16 10:42, 8F
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