Re: [問題] veriog撰寫問題
沿用之前的code
補個rising pulse
是否是你要的?
module add_sub(clk,reset,mod_n,incr,decr);
input clk,incr,decr,reset;
output [12:0] mod_n;
reg [12:0] mod_n;
reg incr_d, incr_2d;
reg decr_d, decr_2d;
wire incr_r = incr_d & ~incr_2d;
wire decr_r = decr_d & ~decr_2d;
always@(posedge clk)
begin
if(reset)
mod_n <= 13'd2000;
else
mod_n <= incr_r ? mod_n-13'd10 :
decr_r ? mod_n+13'd10 : mod_n;
end
always@(posedge clk)
begin
if(reset)
incr_d <= 1'b0;
incr_2d <= 1'b0;
decr_d <= 1'b0;
decr_2d <= 1'b0;
else begin
incr_d <= incr;
incr_2d <= incr_d;
decr_d <= decr;
decr_2d <= decr_d;
end
end
endmodule
--
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