Re: Fatal trap 19: non-maskable interrupt trap while in kernel m
:Hmm, PERR and SERR indicates PCI bus parity errors and other fatal errors.
:I added it to detect broken hardwares. This is the first report of the error
:I have ever got.
:
:Are you sure it has something to do with clearing on-chip memory?
:Do you know how to clear them?
Generally just writing to all the on-chip memory does it, the same way
the BIOS writes to all of ram to initialize the ECC bits when ECC memory
is installed and writes to the cpu cache(s) (for cpus that don't have a
global clear) to fix the cache's internal parity check bits.
It used to be that I/O chipsets (at least for PCs) didn't bother with
ECC or parity for their on-chip ram, but these days most of those chipsets
actually have cpu cores on them which *do*, so they get it almost for
free.
If that is indeed the cause. It could also just be broken hardware :-)
But I suspect it is the memory because Gabor did indicate that his BIOS
was fairly thinly coded on that box.
:> Note that in his commit message he had to turn off write-invalidate.
:> That's a sure sign of on-chip parity checked memory not being initialized.
:
:I thought PERR/SERR is independent of write-invalidate. Could you
:explain more?
:...
:/\ Hidetoshi Shimokawa
:\/ simokawa@FreeBSD.org
Actually I think I'm wrong there. I was reading write-invalidate but
thinking write-combine. write-invalidate should be unrelated.
-Matt
Matthew Dillon
<dillon@backplane.com>
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