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作者 rainstraw 在 PTT [ Electronics ] 看板的留言(推文), 共7則
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[問題] 多design include相同module合成時redefi
[ Electronics ]12 留言, 推噓總分: +2
作者: kramasdia - 發表於 2016/06/23 20:36(9年前)
6F推rainstraw: 你的A B C gate level netlist 應該都有module m,07/02 00:42
7F→rainstraw: 分開syn A,B,C又沒把m當成blackbox, 所以A/B/C_syn.v07/02 00:43
8F→rainstraw: 通通有module m07/02 00:43
9F→rainstraw: DC只跟你講B有重複 可能是因Error太多他已經放棄治療了07/02 00:43
10F→rainstraw: 1. 可以考慮合成時不要放m.v, 當成blackbox07/02 00:45
11F→rainstraw: 2. 既然你都說環境一致了, 把B解體成簡單版本試syn07/02 00:46
12F→rainstraw: 問題繼續發生就拆design直到簡單到爆..總會抓出問題07/02 00:46
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