[北美] 徵entry level ASIC DV工程師消失
又來幫隔壁經理收履歷了 entry level FT position
意者站內信謝謝
身份的話至少需要能在美國合法工作
地點在 San Jose, CA
Responsibilities may include, but are not limited to:
· Partake in definition, design, verification, and documentation for
SoC System on a Chip development.
· Participate in architecture design, logic design, and system
simulation.
· Defines module interfaces/formats for simulation.
· Performs Logic design for integration of cell libraries, functional
units and subsystems into SoC full chip designs.
· Register transfer level coding, and simulation for SoCs.
· Contributes to the development of multidimensional designs involving
the layout of complex integrated circuits.
· Performs all aspects of the SoC design flow from high-level design
to synthesis, place and route, timing and power to create a design database
that is ready for manufacturing.
· Analyzes equipment to establish operation infrastructure, conducts
experimental tests, and evaluates results.
· May also review vendor capability to support development.
You must possess the minimum qualifications to be initially considered for
this position. Preferred qualifications are in addition to the minimum
requirements and are considered a plus factor in identifying top candidates.
Relevant experience can be obtained through school work, classes and project
work, internships, military training, and/ or work experience. This is an
entry level position and will be compensated accordingly.
Minimum Requirements:
· The candidate must possess a MS Degree in Electrical Engineering or
equivalent
Minimum 3 months experience in the following:
· Integrating IPs and cross-functioning with IP teams
· Hardware design, design verification, timing analysis, clock domain
crossing, and lint.
Preferred Qualifications:
· Knowledge of memory system design DDR4/DDR5/LPDDRx
· Knowledge of analog/mixed signal simulations SPICE/AMS
· Synthesis and Timing Closure flows, especially industry tools such
as Design Compiler and PrimeTime.
· Comfortable with scripting languages such as Perl,TCL
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