[求救] 積電作業 HW3 verilog

看板NTUEE113HW作者TommyKSHS (湯米)時間12年前 (2011/12/13 22:52)推噓8(8推 0噓 10→)

留言18則, 6人參與討論串1/1

我跑了 ncverilog +access+r tb_Comparator_51.v lib.v Comparator_51.v 這個指令後出現了 The tool has encountered an unexpected condition and must exit. Contact Cadence Design Systems customer support about this problem and provide enough information to help us reproduce it, including the logfile that contains this error message. TOOL: ncsim 08.20-s024 HOSTNAME: cad32 OPERATING SYSTEM: SunOS 5.10 Generic_118833-24 sun4u MESSAGE: sv_seghandler - SIGSEGV while handling SIGSEGV System task: $fsdbDumpvars file: ./tb_Comparator_51.v line: 52 有哪位先進知道這該怎辦… 原本以為逃離資結就不會有 segmentation fault 了結果連 verilog 都會 segmentation fault 是怎樣… QQQQ -- ╭═══╤═══╮ ╰═╮ ╭═╯ │ │ │╭═和平，土地，麵包═╮ │ │ │ ╭═╧╧╮╤═╤═╮═╤═╤╧╮ │ │ │ │ ││ │ │ │ │ │ ╰═╤═╯ │ │ ││ │ │ │ │ │ │ ╰╧╯╰═══╯╰ ╰ ╰ ╰ ╰ ╰ ─╯ -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.249.36

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vincere

12/13 22:59, , 1^F

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vincere

12/13 23:00, , 2^F

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vincere

12/13 23:00, , 3^F

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