[理工] 一些考古題的問題

看板Grad-ProbAsk作者qwer123073 (NullSpace)時間9年前 (2017/01/31 12:33)推噓3(3推 0噓 26→)

留言29則, 4人參與討論串1/1

1.Every single instruction,when being executed in a n-stage pipelined datapath ,consistently needs n clock cycles before its execution is completely done. (104交大計系第8題) 這句是錯的想問問錯在哪裡如果說管線只放一個指令進去的話不是要n個cycles才會做完嗎？還是我理解錯題目意思其實是說在很多個指令中一個指令平均需要一個cycle？ (理想pipeline CPI = 1) 2.If the size of a block is 1024 bytes and a pointer require 32 bits,in a two- level index system,a file associated with a first-level index block can have a size of up to 256MB. (104交大計系第12題) 這句是錯的想問正確答案應該是多少呢？我的想法是：一個block可以裝 1024/4 = 256 個pointers 所以first-level block中的每個pointer再指出去每個pointer指一個block 所以total size = 256*1024 = 256 "KB" 若有錯請指正 3.Trying to allow some instructions to take fewer cycles does not help,since the throughput is determined by the clock cycle;the number of pipeline stages per instruction affects latency,not throughput. (104交大計系第17題) 這句是對的但我其實選起來怕怕的... 我的想法是首先第一句(Trying to......;) 把一個指令拆成多個stages後每個stage的時間越短整體的throughput就越好第二句(the number......) 嗯...第二句不太懂請各位救我 4.An I/O-bound process spends more time doing I/O than computations and consists of a few long CPU bursts. (105交大計系第3題) 請問這句為什麼錯呢？有什麼反例嗎 5.It is possible to "eliminate" the occurrence of conflict misses by further increaing associativity. (105交大計系第14題) 這句是對的我的理解是關聯度一直上升到最後就變成fully-associative了自然不會有conflict misses 不知道我的想法有沒有錯？ 6.GPUs rely on graphics DRAM chips to reduce memory latency and thereby increase performance on graphics applications. (103清大計系第15題) 這句是錯的請問錯在哪我好像也沒讀到這東西...QAQ 7.再來是我心中一直不解的疑問在寫pipeline題目的時候有時候遇到WB都很猶豫要不要再多stall一個cycle 因為課本說 WB可以前半周期寫後半周期讀那到底要不要在WB stage的時候stall呢？感謝大家 -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 36.233.82.115 ※ 文章網址: https://www.ptt.cc/bbs/Grad-ProbAsk/M.1485837222.A.0AA.html

推