[理工] 幾個計組觀念

看板Grad-ProbAsk作者qwer123073 (NullSpace)時間9年前 (2017/01/23 16:54)推噓7(7推 0噓 20→)

留言27則, 7人參與討論串1/1

有些觀念想請教大家 1.A branch history table buffer is typically indexed by the load instr. address. 這句話是錯的應該怎麼改呢？ 2.Pipeining is a technique that can effectively increase the clock rate. 這句話為什麼是正確的呢？在我的印象中 pipeline不會改善單一指令的latency 而是改善整體的throughput 3.關於3C中的2個C，我想釐清一些觀念： Compulsory misses: 可藉由增大block size來降低compulsory miss 我的想法是這樣的因為block size變大所以block數目變少(index bits數減少) 被access的block再度被access的機率比原本還高了所以冷開機失誤會減少但是如果block size變太大就會增加miss penalty 因為一次要抓一個block 變太大的話抓的成本就高張凡講義有提到 "Very large block could increase miss rate." 這句我想不通為什麼... Capacity misses: 可藉由增加cach size來降低capacity miss 可能造成的負面效果是 access time可能會增加請問為什麼會有這個負面效果呢？ 4.There is no cache coherency problem for the write-through cache since the data are written into the next level of memory,and thus the data are consistent between the two caches. 請問這段話錯在哪裡呢？ 5.A system using a write-through cache as its private cache will not have cache coherency problem since the written data are also updated in the main memory. 請問這句為什麼錯呢？拜託各位了 -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 210.66.250.26 ※ 文章網址: https://www.ptt.cc/bbs/Grad-ProbAsk/M.1485161679.A.C7E.html

推

yupog2003

01/23 16:56, , 1^F

01/23 16:56, 1^F

→

yupog2003

01/23 16:57, , 2^F

01/23 16:57, 2^F

→

yupog2003

01/23 16:57, , 3^F

01/23 16:57, 3^F