[理工] [計組] Data hazard

看板Grad-ProbAsk作者 (LUCENE)時間11年前 (2012/11/09 21:15), 編輯推噓3(3推 0噓 16→)
留言19則, 4人參與, 最新討論串2/2 (看更多)
LD AX,M[100] ;AX←M[100] ADD AX,BX ;AX←AX+BX => AX發生RAW, WAW MOV CX, 1 ;CX←1 ST M[100], AX ;M[100] ← AX => AX發生RAW; M[100]發生WAR ST M[200], BX ;M[200] ← BX ADD CX,M[200] ;CX←CX+M[200] => CX發生RAW, WAW;M[200]發生RAW Suppose the code segment is executed on a pipeline with five stages: instruction fetch, operand fetch, memory read (assuming no need to calculate the effective address), ALU operation, and write back. Hardware will detect any hazard and stall the affected instruction. Draw a space time diagram to show how the code segment is executed through this pipeline. 答案在上面 但看不太懂WAW以及WAR的狀況.. 有高手可以解釋一下嗎.. BTW,我知道WAW和WAR的解釋 但在這題上我完全看不懂 = = -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 203.70.89.179
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11/09 21:37, , 1F
1,2行都寫入AX,3，6行都寫入CX,所以皆有WAW
11/09 21:37, 1F
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11/09 21:39, , 2F
等等，你是不懂程式碼在作啥，還是?
11/09 21:39, 2F
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11/10 00:19, , 3F
LD的目標reg=AX ADD的來源reg=AX.BX--->RAW
11/10 00:19, 3F
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11/10 00:19, , 4F
LD的目標reg=AX ADD的目標=AX-->WAW
11/10 00:19, 4F
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11/10 00:21, , 5F
ADD的目標AX ST的來源AX-->RAW
11/10 00:21, 5F
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11/10 00:22, , 6F
依此類推...記憶體位址我就不知道有沒有datadependency了
11/10 00:22, 6F
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11/10 02:31, , 7F
我的疑問是.. 2行會比1行先寫入到AX嗎..
11/10 02:31, 7F
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11/10 02:31, , 8F
不是要到WB階段才會寫入AX嗎? 這樣不就表示1行一定先寫入AX
11/10 02:31, 8F
推
11/10 02:33, , 9F
RAW WAW WAR有就行了 不一定要發生危障
11/10 02:33, 9F
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11/10 02:35, , 10F
如果一行會先寫入AX 接著換二行寫入到AX..就沒有WAW hazard
11/10 02:35, 10F
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11/10 02:35, , 11F
喔喔 了解
11/10 02:35, 11F
推
11/10 02:36, , 12F
以MIPS來說就只有WAR會發生危障 同樣意思
11/10 02:36, 12F
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11/10 02:38, , 13F
RAW 抱歉
11/10 02:38, 13F
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11/10 02:40, , 14F
但是有RAW WAW WAR不就代表有data hazard?
11/10 02:40, 14F
推
11/10 02:41, , 15F
要視指令級架構而定喔
11/10 02:41, 15F
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11/10 02:44, , 16F
所以你的意思說這一題沒有WAW hazard嗎?
11/10 02:44, 16F
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11/10 02:47, , 17F
此題第一小題是Identify all possible RAW,WAR,WAW hazard.
11/10 02:47, 17F
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11/10 02:49, , 18F
WAW不是hazard是dapadependency!只有RAW才有可能發生
11/10 02:49, 18F
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11/10 02:49, , 19F
hazard
11/10 02:49, 19F
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