[理工] [計組] pipeline stage
refer to a processor with the following number of pipeline stages and
instructions issued per cycle:
pipeline depth issue width
10 4
(1) How many register read ports should the processor have to avoid any
resource hazards due to register reads?
4*2 = 8
(2) If there are no branch mispredictions and no data dependences, what is the
expected performance improvement over a 1-issue processor with the classical
five-stage pipeline? Assume that the clock cycle time decreases in proportion
to the number of pipeline stages.
10/5 * 4 = 8
(3) Repeat Excercis(2), but this time every executed instruction has a RAW
data dependence to the instruction that executes right after it
10/5 = 2
張凡下冊78頁
請問為什麼要這樣算?
謝謝
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