[理工] [離散] 有限狀態機
題目出自97年成大電機
please design/draw a minimum Moore-type state diagram with two inputs,A and
B, and a simple output Z that is 1 if (1) A had the same value at each of the
two previous clock cycles, or (2) B has been 1 since the last time that the
first condition was true. Otherwise, the output should be 0.
順便問一題是 graph coloring
please find a 3 clock cycles scheduled data flow graph(the one like a state
diagram) for the following computations and derive the minimum number of
registers used in the graph using 2 adders and 1 multiplier. Assume both
of the adder and the multiplier have one clock cycle delay.(Hint: using the
graph coloring approach)
r = g + h +i
s = g + c + h*c
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