Re: [理工] [計組] miss latency跟bank conflict

看板Grad-ProbAsk作者jackbll (阿湯)時間14年前 (2011/08/19 23:19)推噓2(2推 0噓 4→)

留言6則, 3人參與討論串2/2 (看更多)

※ 引述《mqazz1 (無法顯示)》之銘言： :cache block size(B) can affect both miss rate and miss latency. Assuming the :following miss rate table, assuming a 1-CPI machine with an average of 1.35 : references (both instruction and data) per instruction, find the optimal block : size given the following miss rates for various block sizes : 8 16 32 64 128 : 8% 3% 1.8% 1.5% 2% : (1) what's the optimal block size for a miss latency of 20*B cycles? 找最佳的block size = 找 memory-stall 最少的 block size memory-stall = (miss rate)*(miss penalty) 8 1.35 * 8 % * (20* 8) 16 1.35 * 3 % * (20* 16) 32 1.35 * 1.8% * (20* 32) 64 1.35 * 1.5% * (20* 64) 128 1.35 * 2 % * (20*128) 因為20 , 1.35都是常數看失誤率乘區塊大小找最小值就好了所以 .... size rate*size 8 0.64 16 0.48 <--min 32 0.576 64 0.96 128 2.56 因此最佳解 16 byte : (2) what's the optimal block size for a miss latency of 24+B cycles? 同上題一樣只是區塊逞罰關係變用加的一樣找延遲最少 SIZE memory-stall 8 1.35 * 8 % * (24+ 8) = 1.35*8% * 32 = 1.35 * 2.56 16 1.35 * 3 % * (24+ 16) = 1.35*3% * 40 = 1.35 * 1.2 32 1.35 * 1.8% * (24+ 32) = 1.35*1.8%* 56 = 1.35 * 1.008 64 1.35 * 1.5% * (24+ 64) = 1.35*1.5%* 64 = 1.35 * 0.96 <-min 128 1.35 * 2 % * (24+128) = 1.35*2% *152 = 1.35 * 3.xx 因此最佳解 64 byte 對了~ 1.35是因為每個指令平均參考記憶體1.35次 : 張凡下冊182頁 : ================ : Assume a memory system that supports interleaving either four reads or four : writes. Given the following memory addresses in order as they appear on the : memory bus: 3, 9, 17, 2, 51, 37, 13, 4, 8, 41, 67, 10, : which ones will result in a bank conflict? : 請問這要怎麼解? : 張凡下冊187頁 : 謝謝這題我也很好奇要怎麼做XD 以上....有錯誤請幫忙指正感激不盡 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.116.112.107

推

mqazz1

08/20 20:28, , 1^F

08/20 20:28, 1^F

→

metalalive

08/24 12:23, , 2^F

08/24 12:23, 2^F

→

metalalive

08/24 12:23, , 3^F

08/24 12:23, 3^F