[理工] [計組]-中山電機
A bus system consists of a multiplexed 32 bit for transferring both
address and data. There are 1G memory locations and 4I/O modules to be
referenced by CPU. A centralized arbitration scheme (No hidden arbitration)
with a clock rate of 40 MHz is used.
Assuming that
(1)Memory latency time (the time required to latch the requestd
data on the bus) =40nsec ,and
(2)Memory word length =4 bytes
(3)CPU always requests data in a block of 4words, and it takes two bus
cycles for bus arbitration and one bus cycle for transferring address
to main memory.
Calculate the effective bus bandwitdth (in Mbytes/sec) if CPU accesses
the 4words at the same time in a Block Data Transfer Mode?
答案
f=40MHz =25ns
傳送4words 需要2+1+4x2+1 =12 clock (想不出來這一部分怎麼求得的）
12 clock =300ns
所以頻寬＝4x4Byte x 1/300ns =53.3Mbyte/sec
麻煩各位高手指點了
謝謝大家
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※ 編輯: bigrat2 來自: 114.33.6.216 (03/24 00:11)
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