[考古] 計算機結構/張貴忠/97上期末
※ [本文轉錄自 FCU_Talk 看板]
作者: justforppt (洨麵人) 看板: FCU_Talk
標題: [考古][資訊][張貴忠][97年上期末][計算機結構][計結]
時間: Wed Jan 14 14:27:05 2009
1. Branch in simple five-stage pipeline
(a)What are the two parts of determining a conditional brancd?
(b)Explain how the branch penalty can be reduced to 1 cycle?
(c)What are the required cost in order to achieve the solution of 1 cycle
penalty?
(d)What are the software solutions to eliminate the branch penalty?
(e)Can we reduce the branch penalty to 0 cycle? If yes,how to? If not,why not
2. Just a brief explanation
(a) What is Temporal locality? What is Spatial locality?
(b) What are the effects if we increase the block size in cache?(suppose the
cache size is fixex)
(c) Howto solve the data hazard for R-type instructions?
3. For a 4KB cache with a block of 16 bytes,how the organizations for caches
with direct-mapped and four-way set associative respecively for 32-bit
input address.
(a) Split the 32-bit address into "tag","index",and "offset" pieces,How many
address bits comprise each piece for each organization? Show the
organization for two chches.
(b) Compute the total bits(including tags and one valid bit) required for
these two structures respectively.
4. A computer architect needs to design the pipeline of a new micro-processor.
She has an example workload program core with 10^6 instructions.Each
instructions takes 100ps to finish.
(a) How long does it take to execute this program core on a nonpipelined
processor?
(b) The current state-of-art micro-processor has about 20 pipeline stages.
Assume it is perfectly pipelined.How much speedup will it achieve
compared to the nonpipelined processor?
(c) Real pipelining isn't perfect,since implementing pipelining introduces
some overhead per pipeline stage. Will this overhead affect instruction
latency,instruction throughput,or both?
5. 給你第五張的電路圖...將其指令的控制訊號的值寫出
RegDst ALUSrc MemtoReg RegWrite MemWrite MemRead Branch ALUOP1,2
R-type
lw
sw
beq
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