[請益] Open collector and Tri-Stating Outputs

看板Electronics作者 (brotherD)時間6年前 (2017/08/07 11:55), 編輯推噓1(1016)
留言17則, 3人參與, 最新討論串1/1
各位好,小弟目前在自修"An Embedded Software Primer"。其中裡面有一些看不懂的疑 問 圖片:http://imgur.com/a/97LLF http://imgur.com/a/9cuOz http://imgur.com/a/xWo9r 在第一張圖片中,the open collector outputs, allows you to attach the outputs of several devices together to drive a single signal. Unlike the usual outputs, which drive signals high or drive them low, the open collector outputs can drive their outputs low or let them float. 想請問一下這一段。open collector outputs可以讓Chip 1跟Chip 2的outputs為low 或 float。是因為在Chip1跟Chip2的輸出有一個inverter嗎? 什麼是usual outputs?是指輸出 沒接其他的外部電路嗎? 在第二張圖片中,If several open collector outputs are attached to the same signal, then the signal goes low if any of the outputs is driving low. open collector outputs不是只有一個嗎?為什麼會有好幾個? 這裡的same signal是指哪 個signal? pullup resistor上的signal嗎? 同樣在第二張圖片中,為什麼一定要有pullup resistor?為什麼沒有的話,INT/會float? pullup resistor是接到VCC,就算沒有這顆電阻,INT/也是high吧? 其中,Note also that you cannot omit the resistor and connect the INT/ signal directly to VCC. If you did this, then you would have a bus fight on your hands as soon as one of the devices tried to drive INT/ low, since the parts that provide electrical power to your circuit would then try to keep INT/ high. 這句的意思是說,如果Chip 1或Chip 2想要給INT/ low,但VCC同時給high會導致bus fight,但是,為什麼加上pullup resistor就不會發生呢? 謝謝前輩們看完這冗長又基本的問題,謝謝。 -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 60.248.26.157 ※ 文章網址: https://www.ptt.cc/bbs/Electronics/M.1502078120.A.7E5.html

08/07 16:49, , 1F
你先了解什麼是open collector跟floating
08/07 16:49, 1F

08/07 16:49, , 2F
就是有 collector的輸出
08/07 16:49, 2F

08/07 16:50, , 3F
wiki就有了
08/07 16:50, 3F

08/19 18:39, , 4F
我用CMOS跟你解釋好了
08/19 18:39, 4F

08/19 18:39, , 5F
你先找個CMOS Inverter電路
08/19 18:39, 5F

08/19 18:39, , 6F
usual output就是用MOS
08/19 18:39, 6F

08/19 18:39, , 7F
輸出LOW時把輸出端往下拉
08/19 18:39, 7F

08/19 18:39, , 8F
輸出HIGH時把輸出端往上拉
08/19 18:39, 8F

08/19 18:39, , 9F
(跟VDD導通或GND導通)
08/19 18:39, 9F

08/19 18:39, , 10F
而open collector(CMOS是open drain)
08/19 18:39, 10F

08/19 18:39, , 11F
則是輸出LOW時靶輸出端往下拉
08/19 18:39, 11F

08/19 18:39, , 12F
輸出HIGH時什麼都不拉
08/19 18:39, 12F

08/19 18:39, , 13F
所以若沒接提昇電阻,輸出端就會是開路的狀態
08/19 18:39, 13F

08/19 18:39, , 14F
這麼做的好處就是兩個O.D.輸出可以接一起而不會造成短
08/19 18:39, 14F

08/19 18:39, , 15F
路(一個HI一個LO時
08/19 18:39, 15F

08/19 18:40, , 16F
形成一個AND閘的概念,只要其中一個輸出LOW則輸出LOW
08/19 18:40, 16F

08/19 18:40, , 17F
,全部都輸出HIGH時才經由提升電阻接到正(MOS開路)
08/19 18:40, 17F
文章代碼(AID): #1PX-IeVb (Electronics)