[問題] FPGA輸出訊號干擾...
各位先進大家好
小弟我進行 Pattern Generator的實驗
因為設計上邊關係,所以經過的電路電路板較多...
造成到後端阻抗上量測到的訊號不佳...(請看下圖)
http://ppt.cc/7Ejy (紅色線為零准位)
訊號准位為: 0~1.8V
頻率為 : 10 MHz
懇請各位先進回答一下小弟問題...
1. 請問該干擾為?
2. 如何濾除該雜訊(我試過鉗位與濾波電容皆無效)
3. 還是需要外加電路?
麻煩請各位解答了...
感謝~
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