[問題] HSPICE問題

看板Electronics作者 (Steve)時間13年前 (2013/01/05 22:28), 編輯推噓0(001)
留言1則, 1人參與, 最新討論串2/2 (看更多)
小弟最近在做SPICE的練習 做到了Non-overlapping Two-Phase Clock Generator的電路 .options post=2 .global VDD GND .MODEL nch NMOS (LEVEL=2 LD=0.250U TOX=365E-10 + NSUB=2.13818E+16 VTO=0.84898 KP=5.7790E-05 + GAMMA=0.8905 PHI=0.6 U0=610.8 UEXP=0.244555 + UCRIT=128615 DELTA=2.0298 VMAX=92227.9 XJ=0.250U + LAMBDA=1.956049E-02 NFS=2.307838E+12 NEFF=1 + NSS=1.0E+12 TPG=1.0 RSH=22.730 CGDO=3.54775E-10 + CGSO=3.54775E-10 CGBO=6.354506E-10 CJ=3.7740E-04 + MJ=0.45890 CJSW=5.1360E-10 MJSW=0.36620 PB=0.800) ******************************************************* .MODEL pch PMOS (level=2 LD=0.250U TOX=365E-10 + NSUB=6.193910E+15 VTO=-0.826989 KP=2.2870E-05 + GAMMA=0.4793 PHI=0.6 U0=241.796 UEXP=0.214214 + UCRIT=19100.4 DELTA=0.859687 VMAX=47972.9 XJ=0.250U + LAMBDA=5.403347E-02 NFS=2.351269E+11 NEFF=1.001 + NSS=1.0E+12 TPG=-1.0 RSH=76.020 CGDO=3.54775E-10 + CGSO=3.54775E-10 CGBO=6.981174E-10 CJ=2.2624E-04 + MJ=0.46650 CJSW=2.3825E-10 MJSW=0.24660 PB=0.700) ***POWER*** VDD VDD GND VDD Vin CLK GND Pulse(0 VDD 0 2n 2n 500n 1200n) ***subckt Circuit*** .subckt inva in out M1 out in VDD VDD pch W=20u L=2u M=1 M2 out in GND GND nch W=8u L=2u M=1 .ends .subckt invb in out M1 out in VDD VDD pch W=6u L=20u M=1 M2 out in GND GND nch W=8u L=2u M=1 .ends .subckt invc in out M1 out in VDD VDD pch W=40u L=2u M=2 M2 out in GND GND nch W=16u L=2u M=2 .ends .subckt NAND 2 3 out M1 out 2 VDD VDD pch W=20u L=2u M=1 M2 out 3 VDD VDD pch W=20u L=2u M=1 M3 out 3 1 GND nch W=8u L=2u M=1 M4 1 2 GND GND nch W=8u L=2u M=1 .ends ***Main Circuit*** x1 CLK N5 inva x2 CLK N8 N2 NAND x3 N2 N3 invb x4 N3 N4 invb x5 N4 PHI_1 invc x6 N4 N5 N6 NAND x7 N6 N7 invb x8 N7 N8 invb x9 N8 PHI_2 invc C1 PHI_1 GND C1 C2 PHI_2 GND C2 ***Simulate*** .tran 1n 3.5u .meas tran ts1 trig V(PHI_2) val='VDD*0.5' fall=1 +targ V(PHI_1) val='VDD/2' rise=1 .meas tran ts2 trig V(PHI_1) val='VDD*0.5' fall=1 +targ V(PHI_2) val='VDD/2' rise=1 .temp 25 .param VDD=5 C1=2p C2=2p .alter .temp 70 .param VDD=4.5 C1=4p C2=4p .alter .temp 0 .param VDD=5.5 C1=1p C2=1p .end 跑出來的PHI_1和2沒有明顯的電容效應,但我同學和我寫的電路類似, 跑出老師要我們跑出的圖形,想請問我是否哪裡寫錯,還是寫的時候有特地的順序呢? -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 112.104.89.127

01/05 22:39, , 1F
GND不用宣告嗎??
01/05 22:39, 1F
文章代碼(AID): #1Gw3YR-1 (Electronics)
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文章代碼(AID): #1Gw3YR-1 (Electronics)