Re: [問題] OPA模擬，閉迴路看phase margin，對嗎?
※ 引述《windyddd (ddd)》之銘言：
: ※ 引述《coa481 (手機快復活-_-||)》之銘言：
: : 請教各位前輩:
: : 在模擬OPA時，單就該OPA的特性做模擬時，如:
: : 開迴路增益、Phase Margin等，所得到的值
: : 與接成閉迴路(假設直接由輸出接回輸入)所得到值，哪一個才是對的阿??
: : 我試的結果，當我用開迴路模擬的話，Gain很小，很多MOS都在Liner，甚至有off的
: : 而接成閉迴路後，不但Gain上升，PM也穩定約70度
: : 正常而言，應該是失敗吧~可是又會被閉迴路所看到的結果給迷惑了...
: : 特別是有一位業界的朋友，說他們都直接模擬閉迴路，這樣我更迷惑了...
: : 另外，以一個簡單的two-stage OPA來講，假設輸入對用PMOS
: : 那這2顆的body，可以直接接它們的source嗎?
: : (正常不是都要接到最正的電壓?)
: : 請幫我解惑~謝謝。
: I recommend you read Jacob Baker's book on Operational Amp. I
: He clearly depicts every detail on testing open loop gain,
: freq. response, compensation..so on so forth.
: Good Luck
Why do we need to know the phase margin?
The system is unstable because it is a closed-loop system.
That's why I said that it doesn't make sense to talk about the phase margin
when the system is an open-loop system.
We are suppposed to measure the phase margin of the closed-loop system using
the bode plot of the loop gain rather than the open-loop gain or the closed-loop
gain. When the feedback factor, beta, is equal to unity, it's a so-called worst
case. Under this condition, the loop gain is equivalent to the open-loop gain.
That's why somebody measures the phase margin of the closed-loop system based on
the open-loop gain. They want to know the phase margin for the worst case.
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