[Multicore] Homework #1, Due Next Wednesday (10/15)
第一題就交給我找資料了(目前我最閒XD)
2、3你們再協調吧!
有問題隨時回報到板上討論!
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The purpose of this homework is to review first two chapters and have you
survey the systems on the market. Please complete the following exercises on
paper with handwriting and drawing.
1.
(50%) For each of the following three multicore processors: (a) Intel Core 2
Quad 6600 (b) Sun UltraSPARC T2 and (c) IBM Cell,
a.
(15%) Sketch diagrams to show the CPU/cache/memory architecture.
b.
(15%) Describe the interconnect between processor cores and memory. What is
the bandwidth for the interconnect?
c.
(20%) Describe the cache coherence mechanism, and explain the reasons behind
its design.
2.
(25%) Draw a diagram and briefly describe how the MESI cache coherence
protocol works. Explain the differences between M and E states.
3.
(25%) How does Sun implement its virtual machine manager in UltraSPARC T2?
What applications would make use of the VMM?
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10/10 08:27, , 1F
10/10 08:27, 1F