[請問] 基礎電學

看板ask作者AquaEnergy (Desperate Houseboy)時間10年前 (2015/11/15 17:02)推噓5(5推 0噓 10→)

留言15則, 3人參與討論串1/1

要看一段說明卻看不懂 Thus at every clock edge, when the potential changes, current flows through the device until it reaches the next steady state. The faster the clock is switching, the more current is flowing, therefore faster clocking implies more power consumed by the embedded processor. Depending on the device, the clock circuit is responsible for consuming between 50% and 90% of dynamic device power. 我自己翻譯的是在每個clock edge，當電位改變時，電流會不斷通過裝置直至達到穩定狀態 clock交換越快，電流流動越多。因此時脈越快，嵌入式系統消耗電力越多 clock circuit... 這段話應該是蠻簡單的，但不是念電類相關的還真的有點難懂請問能解答一下這段話的意思嗎？謝謝！ -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 182.234.148.56 ※ 文章網址: https://www.ptt.cc/bbs/ask/M.1447578134.A.986.html

推

azdy

11/15 17:30, , 1^F

11/15 17:30, 1^F

→

azdy

11/15 17:30, , 2^F

11/15 17:30, 2^F

→

azdy

11/15 17:30, , 3^F

11/15 17:30, 3^F