[徵才] AMD 徵serdes IP and system architect

看板Tech_Job作者 (周先生)時間1月前 (2024/05/17 00:34), 編輯推噓4(409)
留言13則, 9人參與, 1月前最新討論串1/1
組裡招人 在台北或新竹都可以 title 範圍根據面試結果可從MTS-SMTS-PMTS 相對的薪資範圍從240-450萬(8萬-15萬美金,base salary) RSU以及sign on bonus 另計 有興趣的請跟我聯絡 email: chihhsun@amd.com 以下是Job Description Job Title: SerDes IP and System Architect, Modeling and Simulations Job Description: The SerDes Architecture and Modeling Group has responsibilities in generating robust SerDes architecture and algorithms, creating silicon and system level specifications, developing and verifying SerDes design models, developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon. We’re looking for a system architect to join a fast paced transceiver design team. Our team stays ahead of the technology curve to deliver world-class programmable transceiver solutions for multiple FPGA platforms, supporting over 20 protocols with thousands of customer applications. The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas: ‧ Signal processing, data coding, and FEC algorithms ‧ SerDes architecture development including equalizers and time recovery for NRZ and PAM4 systems ‧ Behavioral modeling of different blocks in transceivers ‧ Familiarity with optical link analysis and evaluation is a plus ‧ Presenting design trade-off analyses and implementation recommendations with custom circuit designers Job Requirements: ‧ MSEE a must and Ph.D. preferred, with minimum of 5 year working experience ‧ Signal modulation, coding, and FEC knowledge and experience ‧ Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred ‧ Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc. ‧ ADC based SerDes architecture experience is a plus ‧ Experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus and familiarity with Simulink/Matlab and C/C++ programming ‧ Experience with lab equipment for high-speed digital systems ‧ Good understanding of high speed signal integrity issues ‧ Excellent technical communication skills (presentations and documentation) ‧ Team player -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 149.199.62.130 (美國) ※ 文章網址: https://www.ptt.cc/bbs/Tech_Job/M.1715877253.A.332.html

05/17 02:40, 1月前 , 1F
之前不是有在找嗎== 有那麼難找噢?
05/17 02:40, 1F

05/17 03:12, 1月前 , 2F
可能人被阿婆和我乾爹的公司搶光了
05/17 03:12, 2F

05/17 04:54, 1月前 , 3F
這跟之前的不一樣 這是有人走要補人
05/17 04:54, 3F

05/17 07:59, 1月前 , 4F
Serdes 機會真多
05/17 07:59, 4F

05/17 11:43, 1月前 , 5F
已經夠好了還能去哪
05/17 11:43, 5F

05/17 21:53, 1月前 , 6F
現在簽PhD還來得及嗎
05/17 21:53, 6F

05/17 22:17, 1月前 , 7F
進amd又不用phd
05/17 22:17, 7F

05/18 03:06, 1月前 , 8F
這應該xilinx的人八 amd serdes主力都換xilinx的人
05/18 03:06, 8F

05/18 03:06, 1月前 , 9F
在主導惹 xilinx裡面本來就一堆phd惹
05/18 03:06, 9F

05/18 03:06, 1月前 , 10F
然後也一堆台灣人
05/18 03:06, 10F

05/18 05:35, 1月前 , 11F
居然能看到教主
05/18 05:35, 11F

05/18 15:33, 1月前 , 12F
教主正確 是之前Xilinx的組 我們組目前有三個台灣人
05/18 15:33, 12F

05/18 15:34, 1月前 , 13F
組裡總共七人 六個是PHD
05/18 15:34, 13F
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