[徵才] 多家台廠陸廠找digital/analog/RF/PHY已刪文

看板Tech_Job作者qthsin時間3年前 (2020/12/10 16:37)推噓7(7推 0噓 12→)

留言19則, 15人參與討論串1/1

不收站內信多方科技找Digital IC Design Engineer 工作內容 - Plan design architecture. - Develop high quality digital design. - Be familiar with IC design flow. 要求 - Proficient in Verilog coding and verification. - Experienced in front-end IC design flow. 加分項 - Experienced in C language. - Experienced in scripting language. - Distinguished organizing abilities. - Outstanding problem analysis and debugging skills. 年資:3年即可試地點:新竹年薪:150-220萬(結構為現金+股權) 敦泰找Senior Analog IC Design Engineer 1. 開發IDC(TDDI)中Touch 類比電路設計 2. 協助產品量產相關事項條件: 1. 熟悉類比電路設計及Tool (Spice, IC6 等) 2. 熟ADC, Charge amp, OPamp 佳年資: 5年以上地點: 竹科年薪:依學經歷談敦泰找Senior Digital IC Design Engineer 1. Touch 相關數位電路設計 2. 電路模擬與驗證 3. 使用 STA/ATPG/nLint front-end 相關分析 tool 4. 協助處理量產良率及客訴問題條件 1. 熟悉 Verilog HDL, 了解 front-end design flow, 具有實做經驗 2. 了解 AMBA架構 , 有使用過 8/16/32bit MCU經驗 3. 優先考慮具備下列任一條件者 3-1 略懂類比電路 (ADC/DAC/BGP/LDO/OSC) 3-2 具有建立CP量產 pattern經驗年資: 5年以上地點: 竹科年薪:依學經歷談創意電子找DDR/HBM PHY Design Engineer(Analog或 Digital皆可 ) 1. HBM / DDR IO circuit design, layout reviewing and PI/SI simulation. 2. HBM / DDR PHY design, implementation and verification. 3. Needs co-work with controller designer. 4. Needs prepare verilog model/lef/lib/db/gds/spi to customer. 5. Needs prepare PR guide and discussion with APR engineer. 條件 1. Familiar with Prime Time. 2. Had experience with backend flow. (At least once tape out experience ). 3. Familiar with verilog is better. 4. Had analog circuit knowledge is better. 年資: 5年以上地點: 竹科年薪:依學經歷談創意電子找Senior Mixed-Signal IC Design Engineer 符合以下經驗之一即可 1. PLL/DLL/VCO circuit design 2. ADC circuit design 3. DAC circuit design 4. High Speed SerDes circuit design 加分項 1. 熟 Matlab佳 2. 熟 mixed signal design flow佳 (ex, Inductor extraction, RC extraction, mixed mode simulation) 年資: 5年以上地點: 竹科年薪:依學經歷談通訊陸廠ICOMM找Senior Analog IC Design Engineer ✓ Filter / PGA / TIA ✓ ADC/DAC ✓ charge-pump/band-gap/LDO/op amps ADC/PLL 以上電路設計,量測以及除錯經驗 ✓有先進CMOS 製程（<0.18um）設計經驗尤佳地點: 竹北年薪:200-300萬通訊陸廠ICOMM找Senior RF IC Design Engineer 1. Active RF frontend circuit design experience: PA, antenna switch, LNA, VCO, LO buffer and mixer. CMOS Transceiver building block design and related sub-circuit noise modeling and budgeting. 2. Solid understanding of highly scaled CMOS process and device characteristics, and scalingrelated impact to circuit design. 3. Foundation in RF receiver chain noise/linearity budgeting, level planning, analog filter tradeoff vs converter resolution requirement. 條件 1. RF experience on Wi-Fi MAC 2. RF RX Front End 3. LNA / Mixer / TIA 地點: 竹北年薪:200-300萬驅動IC陸廠Chipone找Senior Analog Engineer 1. Analog IP 設計 2. 高速 interface IP設計 3. Whole Chip 整合條件 1. 熟悉類比 IC電路 2. 熟悉 IC Design flow & skill (Hspice、 nanosim、 XA、 finesim、 laker...) 3. 熟悉 LDO, Bandgap, Filter, TX, RX, PLL, DLL, CDR...etc.等類比電路設計 4. 有面板驅動IC設計相關尤佳(有驅動IC設計經驗的Digital Engineer也可試) 地點: 台元年薪:底薪200-300萬歡迎技術背景吻合又有興趣的人才寄履歷到lisa.hsieh@talentplusco.com -- ※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 125.227.177.170 (臺灣) ※ 文章網址: https://www.ptt.cc/bbs/Tech_Job/M.1607589424.A.DDF.html

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