[即時] ASP-DAC
好像除了當事人 知道的人不多
我就搶頭香賀一下
冠賢的
TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders
信瑋、仲鈞、元凱的
Blockage-Avoiding Buffered Clock Tree Synthesis for Clock Latency-Range and
Skew Minimization
兩篇都上囉
// (聽說我們lab接受率是100% 又是一項新紀錄了?! 科科)
恭喜他們啦^^
總算沉冤得雪!!!! (這兩篇都是ICCAD早就該上的paper)
--
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