[情報] Upcoming IEEE Short Course on Fractional-N PLL design
Dear Sir/Madam,
The IEEE SSCS Taipei Chapter has invited Professor Michael Perrott of
MIT to give a short course in Hsinchu (NCTU) and Taipei (NTU) on March
28th and 29th, respectively. Please see below or the attached files
for further
information. To take advantage of a lowered registration fee, please
register and send your payment before March 18.
SSCS Taipei Chapter
----------- IEEE SSCS Taipei Chapter Short Course -----------
"Design, Simulation, and Bandwidth Extension Methods for Fractional-N
Frequency Synthesizers"
Michael Perrott, Assistant Professor, MIT
場次
<第一場> 國立交通大學光復校區電子與資訊大樓國際會議廳
3月28日(星期一) 9:30~12:00，14:00~16:30
<第二場> 國立台灣大學應用力學館國際會議廳
3月29日(星期二) 9:30~12:00，14:00~16:30
報名方式 一律上網報名 (http://powereric.ee.ntu.edu.tw/~sscs/lectures)
報名費用 (含講義、午餐及點心，恕不退費)
IEEE Member Non-IEEE Member
業界 3/18 前 3500 4500
3/18 後 4500 5500
教師 3/18 前 1000 1500
3/18 後 1500 2000
學生 500 1000
繳費方式
(1) 請將支票或匯票掛號寄到『10617台北市大安區羅斯福路四段一號 國立台灣大學電機二館348室 李孋倫小姐收』。
(2) 支票或匯票抬頭『李孋倫』。
(3) 請在支票或匯票背面用鉛筆註明『單位』、『姓名』及『報名序號』。
(4) 欲享有提早報名優惠者，請務必於3月18日前將支票或匯票寄達。
洽詢辦法
(1) 電話: (02)2363-5251 ext.367，李孋倫小姐。
(2) Email: necoppp@cc.ee.ntu.edu.tw
主辦單位 IEEE SSCS Taipei Chapter
協辦單位 國立台灣大學電子工程研究所
台大系統晶片中心
課程大綱
An outline of the course is as follows. The first two hours will focus on the
simpler integer-N synthesizer structure with respect to basics of its
operation,
modeling, design at the system level, and noise analysis. With the integer-N
background in place, the remaining 3 hours will focus on the fractional-N
synthesizer structure with respect to basics of its operation, modeling,
design,
behavioral simulation, noise analysis, and bandwidth extension techniques. In
particular, the topic of bandwidth extension will be examined through
presentation of a new fractional-N architecture that utilizes a newly proposed
quantization noise cancellation method to increase the PLL bandwidth by a
factor
of ten while maintaining excellent noise performance. Calculated, simulated,
and measured results of a custom 0.18贡m CMOS integrated circuit will be
compared to give a sense of the accuracy of the design and simulation methods
and the viability of the architectural approach. Applications of fractional-N
synthesizers within GMSK modulators and clock and data recovery circuits will
then be covered, and then the course will wrap up with a brief discussion of
future research directions.
主講人簡介
Michael H. Perrott received the B.S. degree in Electrical Engineering from New
Mexico State University, Las Cruces, NM in 1988, and the M.S. and Ph.D.
degrees
in Electrical Engineering and Computer Science from Massachusetts Institute of
Technology in 1992 and 1997, respectively. From 1997 to 1998, he worked at
Hewlett-Packard Laboratories in Palo Alto, CA, on high speed circuit
techniques
for Sigma-Delta synthesizers. In 1999, he was a visiting Assistant
Professor at
the Hong Kong University of Science and Technology, and taught a course on the
theory and implementation of frequency synthesizers. From 1999 to 2001, he
worked at Silicon Laboratories in Austin, TX, and developed circuit and signal
processing techniques to achieve high performance clock and data recovery
circuits. He is currently an Assistant Professor in Electrical Engineering and
Computer Science at the Massachusetts Institute of Technology, and focuses on
high speed circuit and signal processing techniques for data links and
wireless
applications. (http://www-mtl.mit.edu/~perrott)
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