[理工] [計組]-台大資工101 CPU Performance
Part II第2題
[CPU Performance]
Calculate the performance of a processor taking into account stalls due to
data cache and instruction cache misses.
‧The data cache has a 92% hit rate and a 2-cycle hit latency. Assume that
latency to memory and the cache miss penalty together is 100 cycles.
‧The instruction cache has a hit rate of 90% with a miss penalty of 50 cycles.
Assume the load never stalls a dependent instruction and assume the
processor must wait for stores to finish when they miss the cache.
Finally, assume that instruction cache misses and data cache misses never
occur at the same time.
(a) Calculate the average memory access latency for the data cache.
(b) Assume the base CPI using a perfect memory system is 1.0. Calculate the
additional CPI of the pipeline due to the Instruction cache stalls.
(c) Same as (b), but calculate the additional CPI due to the data cache stalls.
(d) Assume 30% of instructions are loads and stores. Calculate the overall CPI
for the machine.
Ans:
(a) AMAT = 2 + 0.08 * 100 = 10
(b) The additional CPI due to instruction cache stalls = 1 * 0.1 * 50 = 5
(c) Suppose 30% of instructions are loads and stores.
The additional CPI due to data cache stalls = 0.3 * 0.08 * 100 = 2.4
(d) Overall CPI = 1 + 0.3 * 0.08 * 100 + 1 * 0.1 * 50 = 8.4
請教各位大大，為何(d)的Overall CPI不需要加上2-cycle hit latency
有爬了之前的文但並沒有看到相關的討論，
想了很久也沒想到合理的解釋，
麻煩各位大大了！
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※ 編輯: leviliang (39.12.110.193), 02/04/2019 11:32:13
推
02/04 14:04,
6年前
, 1F
02/04 14:04, 1F
我後來繼續算別題，
發現雖然很多都需要hit latency計算在內，
不過通常是因為分為L1與L2的hit latency，
所以Overall CPI的base CPI才需要使用hit latency來計算。
但這題卻是只有data與instruction cache，
且一開始僅提供data cache的hit latency。
後來(b)已給定base CPI=1，
這應是代表data cache與instruction cache的total hit latency
如此解釋，應該就合理了吧
推
02/04 17:56,
6年前
, 2F
02/04 17:56, 2F
同意b大...
※ 編輯: leviliang (39.12.110.193), 02/04/2019 18:24:47