[計組] pipeline疑問 交大102
最近讀到pipeline有些疑問
希望板上的大大能幫小弟解答
1.) load-use data hazard
在白算盤上看到的forwarding hardware 可分成以下四種情況
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
想請問load-use的情況使用stall+forwarding來解決的話
其中forwarding 可否歸類於上述四種
還是白算盤上的forwarding hardware並沒有寫出這種情形的實作
2.)題目如下
http://i.imgur.com/uERHSsL.jpg
小弟有參考到前面討論的文章
請參考這篇#1KCePaVb (Grad-ProbAsk)
也更正了a,b小題的答案
但做到這題的「分支是否發生在ID階段決定」和解答以及先前參考文章算得不同,看了許
久仍不確定哪裡錯
以下是我做出來的答案
http://i.imgur.com/iEKKZdN.jpg
有想過是不是在ID階段決定的前提是拿到正確的$s1
但如果等到C6的EX再從C5前饋過來亦可正常執行beq指令?
麻煩板上大大幫忙解惑
感激不盡
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