[理工] 計組 pipeline 問題
今天唸到這個問題
三年前有人在板上問過了
但是我看了還是搞不太懂
請各位幫忙指點一下各個選項要表達的意思
如果有張凡課本可直接參考上冊P437.P438的練習題
題目:A group of students have been debating the efficiency of five-stage pipel ine when one student pointed out that not all instructions are active in every stage of the pipeline.After deciding to ignore the effects of hazards,they ma de the following five statements.Which ones are correct?
1.Allowing jumps,branches,and ALU instructions to take fewer stages than the f ive required by the load instruction will increase pipeline performance under all circumstances.
2.Trying to allow some instructions to take fewer cycles does ont help,since t he throughput is determined by the clock cycle;the number of pipe stages per i nstruction affects latency,not throughput.
3.Allowing jumps,branches,and ALU operations to take fewer cycles only helps w hen no loads or stores are in the pipeline,so the benefits are small.
4.You cannot make ALU instructions take fewer cycles because of the write-back of the result,but there is some opportunity for improvement.
5.Instead of trying to make instructions take fewer cycles,we should explore m aking the pipeline longer,so that instructions take more cycles,but the cycles are shorter.This could improve performance.
ANS:2 and 5 are correct
--
※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 42.72.46.54
※ 文章網址: https://www.ptt.cc/bbs/Grad-ProbAsk/M.1472209879.A.1E7.html
推
08/26 23:24, , 1F
08/26 23:24, 1F
→
08/26 23:25, , 2F
08/26 23:25, 2F
推
08/27 01:29, , 3F
08/27 01:29, 3F
→
08/27 01:29, , 4F
08/27 01:29, 4F
→
08/27 01:29, , 5F
08/27 01:29, 5F
→
08/27 01:29, , 6F
08/27 01:29, 6F
→
08/27 01:29, , 7F
08/27 01:29, 7F
→
08/27 01:29, , 8F
08/27 01:29, 8F
→
08/27 01:29, , 9F
08/27 01:29, 9F
→
08/27 01:29, , 10F
08/27 01:29, 10F
→
08/27 01:29, , 11F
08/27 01:29, 11F
→
08/27 01:29, , 12F
08/27 01:29, 12F
推
08/27 01:31, , 13F
08/27 01:31, 13F
→
08/27 01:31, , 14F
08/27 01:31, 14F
→
08/27 11:29, , 15F
08/27 11:29, 15F
討論串 (同標題文章)
完整討論串 (本文為第 1 之 2 篇)：
