[理工] [計組] 記憶體與cache
Assume the following 8-bit address sequence generated by the microprocessor
The cache uses 4 bytes per block. Assume a 2-way set assocative cache design
the uses the LRU algo. (with a cache that can hold a total of 4 blocks).
Assume that the cache is initially empty.First determine the TAG,SET,BYTE
OFFSET fields and fill in the table above. In the figure below ,clearly mark
for each access the TAG,Least Recently Used(LRU) ,and HIT/MISS information
for each access.
題目表格如下：
http://imgur.com/s4EJ2Gd,b6uUEAY
答案如下：
http://imgur.com/5IOBuCx
我的想法：
題目提到總共有4個blocks ，所以我們不是需要4=2^2 ，兩個bits去表示是哪個block嘛？
答案Index那邊只有一個表示，覺得有點小小奇怪。感謝各位先進了！
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