[理工] [計組]-中正97-電機 解答討論(高手請進QQ)
因為逼近考試了 整理爬文的一些討論
再加上自己寫的解答 (不一定對 請高手指教)
希望以文會友
吸引更多的中正電機的題目討論
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中正電機 97 計組
1.http://www.badongo.com/pic/5433069
第一大題的第一小題a
題目問說要增加單一周期datapath..能夠支援swi指令,請畫出需要增加的線和多工器
Ans:應該是在寫入記憶體那邊 放一個多工器來選擇從暫存器寫入
或是從Sign-extend的immediate值寫入
(這邊個人意見 應該是ALU輸出?而非直接immediate值?)
b.
RegDst:1,RegWrite:1,ALUSrc:1,ALUOp:00,PCSrc:0,MenWrite:1,
MemRead:0,MemToReg:0,"MemWriteSrc:0(從暫存器)"
2.Consider a program with the fpllowing instruction mix:
instruction type frequency
Load 25%
Store 15%
Branch 20%
ALU 40%
suppose any miss will cause a stall, please compute the CPI of this program
running on a pipelined machine with no instruction cache misses, no hazards,
a 98% data cache hit rate, and a miss penalty of 50 clock cycles.
no instruction cache misses,no hazards
這樣CPI是多少?1嗎?
data cache miss rate=2%
CPI=1+0.02*(0.25+0.15)*50=1.4
有錯請指正(原po算法
我的算法是 1.5*25%+1*15%+1.25*20%+1*40 (base CPI)
再加上0.02*(0.25+0.15)*50 =1.575
3.In MIPS programs, the current PC is copied to an EPC register once
interrupt occurs. It's possible to write the current PC to register
$ra just like the jal instruction? Why?
我的想法是中斷是將"發生中斷指令的位址存在EPC",所以存的PC值剛好是PC
jal存的位址是存下一個指令的位址(PC+4) 所以答案是不可能
4.Suppose a machine uses 32-bit physical address
If we consider a 2 way set-associative cache with 10 bit cache index and
32-byte cache blocks.
please calculate:
(a)The number of blocks in the cache.
(b)The size of the block offset.
(c)The size of the tag.
我的答案是
tag=17 bit index=10 bit block offset=5 bit
(a)2048
(b)2048* 5 bit=10240 bit
(c)2048*17 bit=34816 bit
5,6,7題有下文了再說 或有高手請賜教^____^"
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