[理工] [計組] 98中央資工

看板Grad-ProbAsk作者 (問題寶寶。請多包容,謝謝)時間13年前 (2012/10/09 00:11), 編輯推噓0(000)
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Try to use the following multiplexers(i,e.,c=0 d=a,and c=1 d=b) to design a combinational shifter that can shift 0-3 bits. Assume that both the input data and output data of your shifter have 4 bits. 2 control bits are used to determine the shift amount. a b | | v v ------------------ | | | |<---c | | ------------------ | v d 問題: 想請問這題要如何寫出truth table及怎麼畫出電路圖出來?謝謝。 感謝各位耐心看完題目,謝謝。 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 123.193.221.223
文章代碼(AID): #1GSliqzm (Grad-ProbAsk)