[理工] [計組] forwarding signal

看板Grad-ProbAsk作者 (numin)時間14年前 (2012/09/15 21:48), 編輯推噓8(8038)
留言46則, 4人參與, 最新討論串1/1
問題:(張凡老師課本下冊p39練習) Problems in this exercise refer to the following sequences of instructions,and assume that it is executed on a five-stage pipelined datapath: ---------------------------------------------------- | Instruction sequence | ---------------------------------------------------- | | lw $1,40($6) | | add $1,$5,$3 | | | add $2,$3,$1 | | sw $1,0($2) | |a.| add $1,$6,$4 |b.| lw $1,4($2) | | | sw $2,20($4) | | add $5,$5,$1 | | | and $1,$1,$4 | | sw $1,0($2) | |--------------------------------------------------- (4)If there is forwarding, for the first five cycles during the execution of this code,specify which signals are asserted in each cycle by hazard detection and forwarding units. 解答: The outputs of the hazard detection unit are PCWrite,IF/IDWrite,and ID/EXZero.IF/IDWrite is always equal to PCWrite,and ID/EXZero is always the opposite of PCWrite. We will only show the value of PCWrite for each cycle. The outputs of the forwarding unit is ALUin1 and ALUin2, which control Muxes select the first and second input of the ALU. ----------------------------------------------------------------- | | Instruction sequence | 1 2 3 4 5 | Signals | ----------------------------------------------------------------- | | lw $1,40($6) | IF ID EX ME WB |1:ALUin1=X,ALUin2=X | | | add $2,$3,$1 | IF ID ** EX |2:ALUin1=X,ALUin2=X | |a.| add $1,$6,$4 | IF ** ID |3:ALUin1=0,ALUin2=0 | | | sw $2,20($4) | IF |4:ALUin1=X,ALUin2=X | | | and $1,$1,$4 | |5:ALUin1=0,ALUin2=1 | |---------------------------------------------------------------- | | add $1,$5,$3 | IF ID EX ME WB |1:ALUin1=X,ALUin2=X | | | sw $1,0($2) | IF ID EX ME |2:ALUin1=X,ALUin2=X | |b.| lw $1,4($2) | IF ID EX |3:ALUin1=0,ALUin2=0 | | | add $5,$5,$1 | IF ID |4:ALUin1=0,ALUin2=2 | | | sw $1,0($2) | IF |5:ALUin1=0,ALUin2=0 | ----------------------------------------------------------------- 想請問解答上Signals的以下四種情況表示什麼意思,如何設定? (1)ALUin1=X,ALUin2=X (2)ALUin1=0,ALUin2=0 (3)ALUin1=0,ALUin2=1 (4)ALUin1=0,ALUin2=2 感謝各位耐心看完題目及問題,謝謝。 ※ 編輯: numin 來自: 123.193.221.223 (09/15 21:55)

09/16 02:08, , 1F
ALUIN1跟2應該就是ALU前的三對一多工器
09/16 02:08, 1F

09/16 02:11, , 2F
前兩個CYCLE都還沒到ALU當然設X
09/16 02:11, 2F

09/16 02:16, , 3F
第四個cycle因為前面是lw 會有load-use 要加個nop
09/16 02:16, 3F

09/16 02:18, , 4F
第五個cycle lw前饋$1給add的$1 設0,1
09/16 02:18, 4F

09/16 02:20, , 5F
b的話一樣 第4個cycle add前饋$1給sw的$1 設0,2
09/16 02:20, 5F

09/16 02:20, , 6F
第五個cycle sw一定不會有前饋 所以設0,0
09/16 02:20, 6F

09/16 02:22, , 7F
為什麼要這麼設可以看課本介紹前饋的偵測碼那頁
09/16 02:22, 7F

09/16 19:09, , 8F
感謝B大的回答。
09/16 19:09, 8F

09/16 19:10, , 9F
我研究了一下,可是還是看不太懂兩個多工器ForwardA和
09/16 19:10, 9F

09/16 19:11, , 10F
ForwardB到底是代表什麼...課本上說的first ALU operand和
09/16 19:11, 10F

09/16 19:14, , 11F
second ALU operand不曉得是指什麼...上面B大說的我大概已經
09/16 19:14, 11F

09/16 19:14, , 12F
懂了,可是還是不知道為什麼ALUin1都是0,然後在思考ALUin2
09/16 19:14, 12F

09/16 19:16, , 13F
我就會完全卡住...看著課本上的Mux設定也完全有看沒有懂,
09/16 19:16, 13F

09/16 19:18, , 14F
可否請B大再解釋的更清楚...因為我真的看不懂這裡...謝謝。
09/16 19:18, 14F

09/16 21:13, , 15F
CC1,CC2的時候 指令還沒到stage3所以都是X,X
09/16 21:13, 15F

09/16 21:15, , 16F
CC3的時候不需要forward 所以ALU1=0 ALU=0
09/16 21:15, 16F

09/16 21:16, , 17F
CC3 因為load use dara hazard 所以exe的控制線都被清成0
09/16 21:16, 17F

09/16 21:19, , 18F
打錯= = cc3 的時候lw在cc3 不須forward 所以都為0
09/16 21:19, 18F

09/16 21:21, , 19F
CC4 因為load use 在stage3的是bubble pcwrite 所以都X,X
09/16 21:21, 19F

09/16 21:33, , 20F
in1都是0的原因是因為 兩題前饋的來源暫存器都是rs
09/16 21:33, 20F

09/16 21:34, , 21F
說錯 都是rt
09/16 21:34, 21F

09/16 21:37, , 22F
rs暫存器都沒有產生前饋當然就設0囉
09/16 21:37, 22F

09/16 22:29, , 23F
不好意思,我還是不懂...想再請教一下g大,B大..
09/16 22:29, 23F

09/16 22:30, , 24F
附上圖http://ppt.cc/lgbm 我現在卡住的地方是在ALU前的兩個
09/16 22:30, 24F

09/16 22:32, , 25F
mux,不曉得我筆記有沒有做錯,兩個mux的1(代表rt),2(表rs)
09/16 22:32, 25F

09/16 22:35, , 26F
然後我就不懂B大說的因為前饋都是rt,然後rs沒產生就設成0是
09/16 22:35, 26F

09/16 22:36, , 27F
怎麼設的了,感謝各位耐心的講解,謝謝。
09/16 22:36, 27F

09/16 22:39, , 28F
另外想問兩個mux的差別是在哪,看了很久還是搞不懂,謝謝。
09/16 22:39, 28F

09/16 22:49, , 29F
你看一下前一頁的偵測碼吧
09/16 22:49, 29F

09/16 22:49, , 30F
兩個MUX是用來控制 EXE stage 要送進去的alu運算的rs rt
09/16 22:49, 30F

09/16 22:52, , 31F
a符合二版P455第四個偵測碼
09/16 22:52, 31F

09/16 22:52, , 32F
b符合第二個偵測碼
09/16 22:52, 32F

09/16 22:53, , 33F
選0,0代表不用forward 0,1表示從MEM/WB 前饋rt到exe stag
09/16 22:53, 33F

09/16 22:55, , 34F
怎麼選 應該就是由forward unit 裡面run page27的危障偵
09/16 22:55, 34F

09/16 23:03, , 35F
請問一下,上面的mux是代表rs暫存器,下面則是rt暫存器嗎?
09/16 23:03, 35F

09/16 23:04, , 36F
其實你有課本 這些不是都有圖可以看嗎...
09/16 23:04, 36F

09/16 23:04, , 37F
沒錯啊~
09/16 23:04, 37F

09/16 23:05, , 38F
感謝B大,g大。
09/16 23:05, 38F

09/16 23:06, , 39F
謝謝兩位耐心的講解,我終於懂了...
09/16 23:06, 39F

09/16 23:06, , 40F
原來我的圖上面標錯,一直想說怎麼上下都有rs,rt,所以才會
09/16 23:06, 40F

09/16 23:07, , 41F
在設定時,一直設定不出來...在B大說出四和二偵測碼後,我才
09/16 23:07, 41F

09/16 23:08, , 42F
發現...感謝B大提醒。也謝謝g大,你在CC4時,解釋用到
09/16 23:08, 42F

09/16 23:10, , 43F
bubble pcwrite時,讓我更加清楚整個過程,再次謝謝兩位。
09/16 23:10, 43F

09/16 23:10, , 44F
回c大,課本前後翻了很多次還是看不懂...看現在終於知道錯在
09/16 23:10, 44F

09/16 23:11, , 45F
哪了,也謝謝你。
09/16 23:11, 45F

09/16 23:13, , 46F
09/16 23:13, 46F
文章代碼(AID): #1GL8SeDv (Grad-ProbAsk)