[理工] [計組]pipeline CPI
What is the average CPI for each of the following 4 schemes taking to execute
the code sequence below?(Note:For the pipeline scheme, there are five
stages:IF,
ID, EX, MEM, and WB. We assume the reads and writes of register file can
occure
in the same clock cycle, and the stall circuits are available.)
add $t3, $s1, $s2
sub $t1, $s1, $s2
lw $t2, 100($t3)
sub $s1, $t1, $t2
(c)(4%)pipelined scheme without data forwarding hardware;
(d)(4%)pipelined scheme with data forwarding hardware(one from EX/MEM to ALU
input, and the other from MEM/WB to ALU input) available.
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我的答案
without forwarding
add $t3, $s1, $s2 IF ID EXE MEM WB
sub $t1, $s1, $s2 IF ID EXE MEM WB
lw $t2, 100($t3) IF * * ID EXE MEM WB
sub $s1, $t1, $t2 IF * * * ID EXE MEM WB
with forwarding
add $t3, $s1, $s2 IF ID EXE MEM WB
sub $t1, $s1, $s2 IF ID EXE MEM WB
lw $t2, 100($t3) IF ID EXE MEM WB
sub $s1, $t1, $t2 IF ID * EXE MEM WB
想法一:
因為管線的CPI=1，也就是執行一個指令要花1個clock cycle
1+1+(1+2)+(1+3)
CPI(no forward)=-----------------= 2.25
4
1+1+1+(1+1)
CPI(forward)=------------- = 1.25
4
但是這個答案跟解答差很遠
於是
想法二:
可能是因為指令數沒有遠大於STAGE數
所以改用
(4+5-1)+5
CPI(no forward)=-----------=3.25
4
(4+5-1)+1
CPI(forward)=-----------=2.25
4
這個答案就跟解答一樣了
所以我想問一下我的想法是否正確
是不是真的因為指令數沒有遠大於stage數才會使得答案錯誤??
然後，甚麼樣的情形之下才會把pipeline的CPI當作1來算勒??
有請高手當一下大心的誕老公公解答一下XDDD
鋼溫!!!
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推
12/25 00:43, , 1F
12/25 00:43, 1F
推
12/25 00:55, , 2F
12/25 00:55, 2F
第一題只差三個nop??
是因為用了前半週寫入後半週讀出吧??
所以是沒有stall的情形下，CPI=1
感謝!!!
※ 編輯: jim055006 來自: 223.142.171.134 (12/25 20:33)