[理工] 計組判斷hazard

看板Grad-ProbAsk作者SiriusCloud (古月小楓)時間14年前 (2011/11/03 12:11)推噓1(1推 0噓 5→)

留言6則, 5人參與討論串1/1

Given a MIPS instruction sequence shown below. Assume the code is executed on a five-stage (IF,ID,EXE,MEM,WB) pipelined MIPS CPU with the capability to finish the register write in the first half cycle and the register reads in the second half cycle 1.sll $t1, $s1,2 2.add $t1, $s2,$t1 3.lw $s3, 100($t1) 4.addi $s3, $s3,1 5.add $zero, $s4,$s3 6.slt $t2 $s3,$zero 7.bne $t2, $zero,L2 ---------------------------------- 我想問 (1.2)有data hazard , 為什麼(1,3)沒有? -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 219.223.252.31

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Byzantin

11/03 12:24, , 1^F

11/03 12:24, 1^F

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RoyalCh

11/03 13:18, , 2^F

11/03 13:18, 2^F

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kimkang

11/03 14:49, , 3^F

11/03 14:49, 3^F