[理工] [計組] multi-level cache

看板Grad-ProbAsk作者 (無法顯示)時間14年前 (2011/07/15 20:29), 編輯推噓2(2推 0噓 5→)
留言7則, 2人參與, 最新討論串1/1
assume that main memory accesses take 70ns and that memory accesses are 30% of all instructions. the following table shows data for L1 caches attached to each of two processors, P1 and P2 L1 size L1 miss rate L1 hit time P1 1 KB 11.4% 0.62ns P2 2 KB 8.0% 0.66ns (2) what is the AMAT for P1 0.62 + (11.4% * 70) = 8.6ns 然後還有另一個數據 13.87 cycles 請問這個是怎麼來的? (3) 這題是P2比較快 為什麼? 謝謝 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 61.228.27.152
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07/15 21:42, , 1F
(2)8.6ns/0.62ns
07/15 21:42, 1F
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07/15 21:42, , 2F
(3)P1 13.87*1.3=18.03
07/15 21:42, 2F
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07/15 21:46, , 3F
0.66+(8%*70)=6.26
07/15 21:46, 3F
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07/15 21:49, , 4F
P2 6.26ns/0.66ns=9.48 9.48*1.3=12.32
07/15 21:49, 4F
推
07/15 21:53, , 5F
P1 CPI=18.03 P2 CPI=12.32 在乘clk cycle time 比較
07/15 21:53, 5F
推
07/17 02:04, , 6F
請問樓上1.3哪來的?
07/17 02:04, 6F
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07/17 22:26, , 7F
指令100%+30%記憶體指令
07/17 22:26, 7F
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