[理工] [計組]-記憶體
題目:A computer system uses two levels of cache L1 and L2.
Level L1 is accessed in one clock cycle and supplies the
data in case of an L1 hit. For an L1 miss,occurring 3%
of the time, L2 is consulted. An L2 hit incurs a penalty
of 10 clock cycles while an L2 miss implies a 100-cycle
penalty.
(2)If we were to model the two-level cache system as a single
cache, what miss rate and miss penalty should we use?
(L2's local miss rate is 25% 且pipeline CPI with no
cache miss is 1)
手邊的答案是: miss rate = 3% * 25%
= 0.75%
miss penalty=1+10+100
=111clock
問題: 為什麼miss penalty 是111呀??
麻煩幫我解答一下 感謝!!
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.134.213.201
推
03/19 17:24, , 1F
03/19 17:24, 1F
→
03/19 19:59, , 2F
03/19 19:59, 2F
推
03/19 20:24, , 3F
03/19 20:24, 3F
→
03/19 20:45, , 4F
03/19 20:45, 4F
推
03/19 21:35, , 5F
03/19 21:35, 5F
→
03/19 22:12, , 6F
03/19 22:12, 6F
→
03/20 12:42, , 7F
03/20 12:42, 7F
→
03/20 12:43, , 8F
03/20 12:43, 8F
→
03/20 12:43, , 9F
03/20 12:43, 9F
推
09/29 16:25, , 10F
09/29 16:25, 10F